Overview

Week 9 focused on precision refinement and rigorous optimization across all engineering tracks. The hardware team dedicated the week to solving the routing bottlenecks of our compact 2-layer PCB layout, while the software team shifted from writing new features to debugging the newly unified codebase. Concurrently, the business track moved into dry-run rehearsals for the upcoming project pitch.

What We Did

• Altium Routing & Design Rule Checks (DRC): Focused entirely on completing the complex trace routing on our 2-layer board. We ran iterative Design Rule Checks in Altium to catch and fix electrical clearance violations, trace width issues, and unrouted nets.
• Unified Codebase Debugging: Conducted extensive testing on the merged software stack using our development kit. We focused on identifying and fixing data race conditions and resolving timing lags in the I2C sensor polling loop.
• Pitch Deck Rehearsals: Conducted initial dry-runs of the pitch presentation. The team reviewed slide transitions, refined the delivery timing, and ensured our technical safety metrics directly aligned with the business value proposition.

Key Decisions

• Strategic Copper Ground Pours: Decided to maximize the ground plane coverage on both the top and bottom layers of the PCB.
  • Why: Because we are restricted to a 2-layer board, filling empty space with a solid copper ground plane is essential to shield our sensitive I2C data lines from the electromagnetic noise generated by the LoRa transmitter.

Challenges

• Trace Bottlenecks and VIAs: Due to the small physical footprint of the enclosure, finding paths for power traces without cutting off signal lines required heavy use of VIAs (vertical electrical connections between layers). This layout puzzle required multiple routing resets to keep the board clean and manufacturable.
• I2C Bus Stalling: During software stress testing, we discovered that if one sensor failed to respond, it would hang the entire I2C bus. We had to implement software timeouts to prevent the code from freezing during real-time operations.

Next Steps

• Complete the final cleanup of the PCB layout, add mounting holes, and generate the manufacturing Gerber files for fabrication.
• Finalize the software timeout logic and ensure data packets are successfully transmitting over the LoRa network.
• Conduct a final, timed dress rehearsal of the pitch deck with peer feedback.