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Week 8 – PCB Layout Routing & Unified System Integration

Overview

Week 8 marked a major integration milestone as the project transitioned from loose breadboard validation to physical PCB design and unified software execution. With the schematic locked, the team shifted its focus to dense board routing in Altium while merging isolated code modules into a single, cohesive software architecture.

What We Did

  • PCB Component Placement & Routing: Formally began the physical layout phase in Altium Designer. We established the mechanical board dimensions, strategically positioned critical components (such as the LoRa antenna and sensors) to minimize noise, and began routing the high-priority I2C and power traces.
  • Codebase Unification: Successfully merged the previously isolated sensor driver and data parsing code into a single, unified codebase on the main GitHub branch, preparing the software for full-system integration testing.
  • Pitch Deck Refinement: Continued developing the business presentation, incorporating our finalized BOM costs, physical board dimensions, and system architecture diagrams into the slide deck.

Key Decisions

  • Commitment to a 2-Layer PCB Layout: Decided to stick with a standard 2-layer PCB stackup (Top and Bottom signal layers) rather than upgrading to a 4-layer board.
    • Why: Keeping a 2-layer design minimizes prototyping manufacturing costs and reduces fabrication turnaround time. To offset potential noise issues, we decided to implement a heavy ground pour on both layers to shield the I2C lines from the LoRa RF signals.

Challenges

  • 2-Layer Routing Constraints: Managing the compact form factor of the VertexShell enclosure on only two layers made trace routing highly complex. We had to carefully manage cross-talk and ensure that return paths for power didn’t cut off or interfere with our sensitive I2C data lines.

Next Steps

  • Complete the remaining PCB trace routing, run Design Rule Checks (DRC), and prepare the manufacturing Gerber files for fabrication.
  • Begin integration testing of the unified software stack on our development hardware kit to iron out any multi-threading or timing bugs.
  • Finalize and practice the pitch deck presentation for upcoming sponsor and stakeholder reviews.