Overview

Week 10 marked a transitional milestone as the team finalized the hardware design for manufacturing and moved into deep software validation. Hardware efforts focused on the meticulous cleanup required to generate production-ready fabrication files, while the software track transitioned into long-term stability testing on the development kit to prepare for the physical boards.

What We Did

• Gerber File Generation & Tape-Out Prep: Completed the final routing modifications on the 2-layer PCB. We added the mechanical mounting holes, cleaned up the silkscreen labels (component designators), and generated the official manufacturing assets, including Gerber files, NC Drill files, and the Pick-and-Place matrix.
• Long-Run Code Stability Testing: Ran the unified software stack continuously on our development kit for extended multi-hour loops. This testing was designed to verify that the newly implemented I2C timeout code successfully prevents system freezes over long deployments.
• Hardware Design Review: Conducted a final comprehensive peer-review of the entire Altium design, verifying trace widths against current requirements and checking pad clearings before exporting the production files.

Key Decisions

• Final Design Freeze for Manufacturing: Enacted a strict hardware design freeze following the final round of Altium Design Rule Checks (DRC), ensuring no last-minute trace modifications could inadvertently introduce electrical shorts prior to manufacturing export.

Challenges

• Silkscreen Legibility vs. Trace Density: Fitting legible text labels for components on a compact, highly dense 2-layer board proved difficult. We had to carefully reposition text labels so they did not overlap with exposed copper vias or solder pads, which would render them unreadable after fabrication.
• Memory Optimization: Extended testing revealed a minor memory leak during continuous LoRa packet construction. The software team had to review the buffer allocation logic to optimize RAM usage on our microcontroller.

Next Steps

• Submit the generated Gerber files to the PCB manufacturer for fabrication and place orders for the physical BOM components.
• Refactor the software’s packet buffering logic to permanently eliminate the memory leaks caught during stability testing.
• Map out the physical assembly and soldering workflow for when the fabricated boards and components arrive.