VertexShell

Week 19 – June 22–27

Mon, 22 Jun 2026 00:00:00 +0000

Overview

Content coming soon.

Planned Work

To be updated.

Key Results

To be updated.

Week 18 – June 15–21

Mon, 15 Jun 2026 00:00:00 +0000

Overview

Content coming soon.

Planned Work

To be updated.

Key Results

To be updated.

Week 17 – Final Submission & Demo Day

Tue, 26 May 2026 00:00:00 +0000

Overview

Content coming soon.

Planned Work

To be updated.

Key Results

To be updated.

Week 16 – Final Deliverables & ElectroDay Preparation

Tue, 19 May 2026 00:00:00 +0000

Overview

Week 16 marked the final phase of the project lifecycle, shifting all efforts toward documentation, marketing, and presentation delivery. With field testing successfully completed, the team focused entirely on compiling our technical data and engineering achievements into our final deliverables—the pitch deck, project showcase poster, and an AI-generated demonstration video—in preparation for ElectroDay.

What We Did

Final Pitch Deck Refinement: Polished our business and technical presentation by incorporating real-world sensor telemetry data, LoRa packet success rates, and photos from our field deployment.
ElectroDay Poster Design: Created a high-resolution, professional showcase poster that visually maps out our 2-layer PCB layout, the unified system architecture, and our field-testing milestones.
AI Video Production: Leveraged AI video generation and editing tools to produce a comprehensive project demonstration video, combining digital system renderings, conceptual animations, and simulated walkthroughs of the VertexShell system in action.

Challenges

Condensing Complex Technical Data: Fitting sixteen weeks of intensive hardware routing, software debugging, and field testing onto a single, cohesive project poster proved difficult. We had to carefully balance visual block diagrams with high-level data summaries to maintain readability for a general audience.
AI Video Prompting and Consistency: Ensuring the AI video generation tool maintained visual consistency for our custom PCB design and specific 3D enclosure shape across different scenes required highly precise asset inputs and prompt iterations.

Next Steps

Complete a final walkthrough of the pitch presentation slides to ensure smooth transitions and timing.
Print the finalized project poster and verify the AI video playback compatibility for the event venue.
Set up the physical hardware display nodes and showcase the fully integrated VertexShell system at ElectroDay.

Week 15 – Real-World Field Testing & System Validation

Tue, 12 May 2026 00:00:00 +0000

Overview

Week 15 marked a major milestone as VertexShell transitioned from a lab prototype to real-world field deployment. Armed with fully assembled hardware, functional software, and our first batch of 3D-printed enclosures, the team conducted environmental and communication testing to evaluate sensor accuracy, LoRa mesh stability, and mechanical durability in a simulated industrial environment.

What We Did

First-Article Enclosure Printing: Finalized our CAD updates using last week’s exact measurements and successfully 3D-printed our first operational, ruggedized PETG enclosure prototypes.
Full-System Integration Assembly: Secured the fully populated custom PCBs inside the new 3D-printed shells, officially assembling our first batch of complete, self-contained VertexShell field nodes.
Environmental Field Testing: Deployed the completed units outdoors in a simulated site environment to evaluate how the physical packaging handles ambient conditions while keeping the sensors properly exposed to air currents.
LoRa Range & Mesh Validation: Conducted extensive distance and obstacle testing with our LoRa transceivers, mapping data packet delivery rates across various ranges to stress-test our multi-node routing protocol.

Challenges

Real-World Signal Obstruction: During distance testing, structural obstacles like concrete walls and metal fencing caused a higher drop in LoRa signal strength than our indoor simulations predicted. This required us to look into tweaking our transmission power settings and optimizing node placement heights to maintain line-of-sight propagation.
Physical Packet Latency: When testing multi-node hops over extended field distances, we noticed an increase in total packet transmission latency, meaning data took longer than expected to jump from the furthest node back to the central hub.

Next Steps

Adjust the software’s LoRa transmission power configurations and routing tables to overcome real-world industrial structural interference.
Optimize the mesh network protocol’s hop timing parameters in code to reduce latency during multi-node data relays.
Compile and analyze all sensor telemetry and packet delivery logs from this week’s deployment to prepare our final technical validation report.

Week 13 – Hardware Arrival & Initial Quality Control

Mon, 11 May 2026 00:00:00 +0000

Overview

Week 13 brought the holding period to an end as our custom-fabricated PCBs and surface-mount components officially arrived at the lab. Keeping to a controlled, methodical pace, the team focused entirely on unboxing logistics, physical inventory management, and conducting baseline electrical safety checks on the raw unpopulated boards before kicking off the assembly phase.

What We Did

Inventory Tracking & Sorting: Unboxed the custom 2-layer PCBs and specific board-level components. We cataloged all microcontrollers, sensors, and passives to ensure our physical inventory completely matched our locked Bill of Materials.
Bare-Board Visual Inspections: Performed detailed visual inspections of the raw PCBs under magnification to check for manufacturing defects, such as trace fractures, misaligned solder pads, or unexpected silkscreen errors.
Electrical Continuity Testing: Utilized a multimeter to run baseline continuity and short-circuit tests on the unpopulated boards, verifying that the power and ground planes were properly isolated before introducing any voltage.

Key Decisions

Phased Assembly Workflow: Decided to adopt a strict, step-by-step soldering strategy rather than populating the entire board at once.
- Why: Soldering and verifying the power regulation circuit first ensures the board safely delivers the correct voltage. This protects our sensitive microcontrollers and I2C sensors from getting fried if there is an underlying hardware issue.
Enclosure Modeling Freeze: Formally chose to hold off on finalizing or printing any 3D enclosure prototypes until the physical board is completely soldered. This ensures we map the exact, real-world vertical clearances and component heights before committing to a 3D print.

Challenges

Manual Inspection Bottlenecks: Checking the tiny footprints of the surface-mount components against the raw PCB pads by hand required extreme patience and precision, slowing down our transition to the soldering iron but saving us from potential manufacturing headaches later.

Next Steps

Set up the soldering station, apply solder paste, and assemble the initial power management subsystem on the first board.
Verify the voltage outputs of the power system using a digital multimeter.
Once the board profile is physically finalized with components, take physical measurements to resume the 3D packaging track.

Week 14 – Physical Board Assembly & Enclosure Metrics

Tue, 05 May 2026 00:00:00 +0000

Overview

Week 14 was a highly productive hands-on week as the project moved into the physical assembly stage. The team fired up the soldering irons to fully populate the custom PCBs, ran initial electrical power tests, and took precise physical measurements of the assembled hardware to finalize the dimensional constraints for our upcoming 3D-printed enclosure.

What We Did

PCB Soldering & Assembly: Executed our phased assembly strategy by manually applying solder paste and soldering the surface-mount and through-hole components onto the custom 2-layer PCBs.
Power-On Electrical Verification: Safely brought up the newly assembled boards using a benchtop power supply. We verified that the voltage regulators successfully stepped down the input power to the correct operating levels required by our microcontroller and I2C sensors.
Physical Enclosure Measurements: With the real-world components now permanently fixed to the board, we utilized digital calipers to measure the exact vertical clearances, connector offsets, and antenna dimensions needed to update our 3D packaging files.

Key Decisions

Component-Height Clearance Buffer: Decided to add an extra 1.5mm of vertical headroom above the highest component (the LoRa module/antenna connection) within our CAD model.
- Why: This ensures adequate internal airflow for heat dissipation and guarantees the physical casing won’t compress or strain any delicate solder joints when snapped shut.

Challenges

Precision Surface-Mount Soldering: Soldering the tight pin pitches of the compact I2C sensors and the main microcontroller by hand required steady precision under a microscope. We had to use fine solder wick to clear a few minor solder bridges that occurred between adjacent sensor pins.

Next Steps

Flash the unified software stack onto the newly assembled physical board and run the first on-board I2C sensor polling tests.
Update the CAD files with our newly collected physical dimensions and print the first true-to-scale 3D enclosure.
Conduct a basic range test with the assembled hardware to check the initial performance of the integrated LoRa antenna.

Week 12 – Shipping Logistics & Extended Enclosure Modeling

Mon, 04 May 2026 00:00:00 +0000

Overview

Week 12 was defined by a slower operational pace as the team waited for the physical PCBs and components to clear shipping transit. To maximize efficiency during this holding period, we shifted our focus toward translating last week’s enclosure concepts into detailed 3D CAD models and expanding our simulated LoRa mesh network testing.

What We Did

Logistics Tracking & Assembly Prep: Monitored the incoming shipments for both the custom PCBs and the board-level components. In the meantime, we prepared our assembly station, organizing soldering tools, solder paste, and stencils to ensure immediate production once the items arrive.
CAD Modeling for 3D Packaging: Advanced our enclosure brainstorming into concrete digital designs. Using CAD software, we modeled the initial 3D outer shell of the VertexShell, incorporating precise alignment standoffs to match the physical mounting holes designed into our Altium PCB layout.
Expanded LoRa Simulation: Continued leveraging our development hardware to test the LoRa mesh architecture, focusing on refining data packet structures to minimize overhead during multi-node relays.

Key Decisions

Enclosure Tolerances: Decided to design the initial 3D-printed enclosure with a slightly generous 0.5mm internal tolerance cushion around the PCB perimeter.
- Why: This accounts for minor physical variations in both the 3D printing process and the raw PCB edges, preventing a tight, forced fit that could stress the board or damage components.

Challenges

Supply Chain Stagnation: The inevitable downtime caused by shipping transit slowed our physical momentum. Managing this project bottleneck required shifting the team’s workload entirely toward digital modeling and software fine-tuning to prevent empty development cycles.

Next Steps

Unbox and physically inspect the PCBs and components upon arrival, running basic multimeter continuity checks on the unpopulated boards.
Export the 3D enclosure CAD files to the 3D printer for our first physical test fit.
Transition from isolated development kit testing to flashing our software onto the custom physical boards as soon as assembly is complete.

Week 11 – PCB Logistics, Component Procurement & Core Testing

Mon, 27 Apr 2026 00:00:00 +0000

Overview

With the hardware design officially sent to production, Week 11 focused on supply chain coordination and launching the next major engineering phases. While our custom PCBs are actively in transit from the manufacturer, the team focused on procuring the specific physical components to populate the boards, kicking off structural 3D packaging designs, and initiating early LoRa mesh network testing.

What We Did

PCB Component Procurement: Executed orders for the specific surface-mount and through-hole components required to populate the incoming custom PCBs. This involved securing the exact manufacturer part numbers for our sensors, microcontrollers, and discrete passives now that the layout is locked.
3D Enclosure Brainstorming: Initiated the conceptual design phase for the physical VertexShell enclosure. The team brainstormed mechanical requirements, focusing on ruggedization, sensor exposure cutouts, and how the internal PCB will mount securely inside the package.
LoRa Mesh Network Testing: Began early-stage network testing for our LoRa mesh configuration using available hardware development kits, laying the groundwork for multi-node communication routing.

Key Decisions

Enclosure Material and Access Path: Decided to target a modular 3D-printed enclosure design using PETG plastic for the initial prototype.
- Why: PETG offers better impact resistance and thermal stability than standard PLA, which is critical for industrial site safety testing, while remaining cost-effective for rapid mechanical revisions.

Challenges

Component Delivery Timelines: Coordinating arrival dates for the PCB components required careful monitoring to ensure that long-lead-time silicon chips do not stall the physical assembly line once the boards themselves arrive.
Mesh Packet Drop: Initial LoRa mesh testing over extended distances revealed minor packet loss during multi-node hops, indicating that we will need to tune our software routing algorithms and transmission power.

Next Steps

Receive the physical PCBs from the manufacturer and inspect them for fabrication defects.
Transition 3D enclosure concepts into initial CAD models and print the first rough-fit prototypes.
Continue refining the LoRa mesh network parameters to stabilize data transmission across simulated node distances.

Week 10 – Tape-Out Preparation & Code Stability Testing

Mon, 20 Apr 2026 00:00:00 +0000

Overview

Week 10 marked a transitional milestone as the team finalized the hardware design for manufacturing and moved into deep software validation. Hardware efforts focused on the meticulous cleanup required to generate production-ready fabrication files, while the software track transitioned into long-term stability testing on the development kit to prepare for the physical boards.

What We Did

Gerber File Generation & Tape-Out Prep: Completed the final routing modifications on the 2-layer PCB. We added the mechanical mounting holes, cleaned up the silkscreen labels (component designators), and generated the official manufacturing assets, including Gerber files, NC Drill files, and the Pick-and-Place matrix.
Long-Run Code Stability Testing: Ran the unified software stack continuously on our development kit for extended multi-hour loops. This testing was designed to verify that the newly implemented I2C timeout code successfully prevents system freezes over long deployments.
Hardware Design Review: Conducted a final comprehensive peer-review of the entire Altium design, verifying trace widths against current requirements and checking pad clearings before exporting the production files.

Key Decisions

Final Design Freeze for Manufacturing: Enacted a strict hardware design freeze following the final round of Altium Design Rule Checks (DRC), ensuring no last-minute trace modifications could inadvertently introduce electrical shorts prior to manufacturing export.

Challenges

Silkscreen Legibility vs. Trace Density: Fitting legible text labels for components on a compact, highly dense 2-layer board proved difficult. We had to carefully reposition text labels so they did not overlap with exposed copper vias or solder pads, which would render them unreadable after fabrication.
Memory Optimization: Extended testing revealed a minor memory leak during continuous LoRa packet construction. The software team had to review the buffer allocation logic to optimize RAM usage on our microcontroller.

Next Steps

Submit the generated Gerber files to the PCB manufacturer for fabrication and place orders for the physical BOM components.
Refactor the software’s packet buffering logic to permanently eliminate the memory leaks caught during stability testing.
Map out the physical assembly and soldering workflow for when the fabricated boards and components arrive.

Week 9 – PCB Layout Refinement & Codebase Debugging

Mon, 13 Apr 2026 00:00:00 +0000

Overview

Week 9 focused on precision refinement and rigorous optimization across all engineering tracks. The hardware team dedicated the week to solving the routing bottlenecks of our compact 2-layer PCB layout, while the software team shifted from writing new features to debugging the newly unified codebase. Concurrently, the business track moved into dry-run rehearsals for the upcoming project pitch.

What We Did

Altium Routing & Design Rule Checks (DRC): Focused entirely on completing the complex trace routing on our 2-layer board. We ran iterative Design Rule Checks in Altium to catch and fix electrical clearance violations, trace width issues, and unrouted nets.
Unified Codebase Debugging: Conducted extensive testing on the merged software stack using our development kit. We focused on identifying and fixing data race conditions and resolving timing lags in the I2C sensor polling loop.
Pitch Deck Rehearsals: Conducted initial dry-runs of the pitch presentation. The team reviewed slide transitions, refined the delivery timing, and ensured our technical safety metrics directly aligned with the business value proposition.

Key Decisions

Strategic Copper Ground Pours: Decided to maximize the ground plane coverage on both the top and bottom layers of the PCB.
- Why: Because we are restricted to a 2-layer board, filling empty space with a solid copper ground plane is essential to shield our sensitive I2C data lines from the electromagnetic noise generated by the LoRa transmitter.

Challenges

Trace Bottlenecks and VIAs: Due to the small physical footprint of the enclosure, finding paths for power traces without cutting off signal lines required heavy use of VIAs (vertical electrical connections between layers). This layout puzzle required multiple routing resets to keep the board clean and manufacturable.
I2C Bus Stalling: During software stress testing, we discovered that if one sensor failed to respond, it would hang the entire I2C bus. We had to implement software timeouts to prevent the code from freezing during real-time operations.

Next Steps

Complete the final cleanup of the PCB layout, add mounting holes, and generate the manufacturing Gerber files for fabrication.
Finalize the software timeout logic and ensure data packets are successfully transmitting over the LoRa network.
Conduct a final, timed dress rehearsal of the pitch deck with peer feedback.

Week 8 – PCB Layout Routing & Unified System Integration

Mon, 06 Apr 2026 00:00:00 +0000

Overview

Week 8 marked a major integration milestone as the project transitioned from loose breadboard validation to physical PCB design and unified software execution. With the schematic locked, the team shifted its focus to dense board routing in Altium while merging isolated code modules into a single, cohesive software architecture.

What We Did

PCB Component Placement & Routing: Formally began the physical layout phase in Altium Designer. We established the mechanical board dimensions, strategically positioned critical components (such as the LoRa antenna and sensors) to minimize noise, and began routing the high-priority I2C and power traces.
Codebase Unification: Successfully merged the previously isolated sensor driver and data parsing code into a single, unified codebase on the main GitHub branch, preparing the software for full-system integration testing.
Pitch Deck Refinement: Continued developing the business presentation, incorporating our finalized BOM costs, physical board dimensions, and system architecture diagrams into the slide deck.

Key Decisions

Commitment to a 2-Layer PCB Layout: Decided to stick with a standard 2-layer PCB stackup (Top and Bottom signal layers) rather than upgrading to a 4-layer board.
- Why: Keeping a 2-layer design minimizes prototyping manufacturing costs and reduces fabrication turnaround time. To offset potential noise issues, we decided to implement a heavy ground pour on both layers to shield the I2C lines from the LoRa RF signals.

Challenges

2-Layer Routing Constraints: Managing the compact form factor of the VertexShell enclosure on only two layers made trace routing highly complex. We had to carefully manage cross-talk and ensure that return paths for power didn’t cut off or interfere with our sensitive I2C data lines.

Next Steps

Complete the remaining PCB trace routing, run Design Rule Checks (DRC), and prepare the manufacturing Gerber files for fabrication.
Begin integration testing of the unified software stack on our development hardware kit to iron out any multi-threading or timing bugs.
Finalize and practice the pitch deck presentation for upcoming sponsor and stakeholder reviews.

Week 7 – Schematic Completion & Breadboard Validation

Mon, 30 Mar 2026 00:00:00 +0000

Overview

Week 7 drove the project to the brink of physical prototyping as the team neared completion of the Altium schematic and successfully validated the core circuit on a breadboard. Concurrently, the software team close-out isolated testing logic, and work began on the business side to frame our progress for upcoming stakeholder presentations.

What We Did

Schematic Capture Finalization: Entered the final stages of the Altium schematic design, successfully linking our custom-built component footprints and wiring the primary electrical connections.
Breadboard Circuit Validation: Assembled a functional prototype on a breadboard to physically confirm the electrical logic, sensor connections, and I2C communication bus integrity before locking the design.
Isolated Code Testing: Advanced the core software logic to near-completion for isolated unit tests, ensuring individual sensor drivers and data parsing routines function reliably before full system integration.
Pitch Deck Initialization: Started drafting the official project pitch deck, translating our technical architecture, finalized BOM costs, and reliability metrics into a compelling business-facing presentation.

Key Decisions

Design Freeze for Layout Preparation: Decided to lock the schematic topology following the successful breadboard validation, allowing the team to transition smoothly into the physical PCB layout phase without introducing scope creep.

Challenges

Breadboard Signal Noise: Encountered minor communication instability during breadboard testing due to loose jumper connections and stray capacitance, which required implementing proper pull-up resistors on the I2C lines to stabilize the signals.

Next Steps

Formally sign off on the Altium schematic and begin the physical PCB component placement and trace routing.
Wrap up the final isolated software tests and prepare the unified codebase for hardware integration.
Refine the pitch deck structure and practice the delivery narrative ahead of sponsor reviews.

Week 6 – BOM Finalization & Custom Hardware Modeling

Mon, 23 Mar 2026 00:00:00 +0000

Overview

Week 6 focused heavily on supply chain consolidation and custom hardware library creation. While the core software codebase continued its steady development, the hardware team dedicated significant effort to generating custom schematic symbols and PCB footprints in Altium to accommodate components lacking manufacturer-provided models.

What We Did

Bill of Materials (BOM) Finalization: Completed and locked the first official draft of the BOM. All critical components, including the CO sensor, IMU, and LoRa module, have been paired with verified manufacturer part numbers and vetted for vendor availability.
Custom Component Library Creation: Generated custom schematic symbols and precise PCB footprints from scratch for the majority of our components, as verified manufacturing models were unavailable.
Ongoing Codebase Development: Continued iterative logic updates within the repository, focusing on optimizing data packets for the upcoming sensor integration testing.

Key Decisions

Component Model Standard: Decided to manually build and double-verify all missing component footprints against IPC standards rather than using unverified third-party community models, ensuring manufacturing reliability.

Challenges

Lack of Pre-made Component Assets: The absence of ready-made Altium symbols and footprints for our specific sensor suite slowed down schematic progress, requiring intensive datasheet cross-referencing to map physical dimensions and pinouts accurately.

Next Steps

Begin linking the newly created custom component footprints to the schematic and officially kick off the Altium board layout.
Deploy the finalized BOM for initial component purchasing.
Run communication loop tests using the I2C bus on the development hardware.

Week 5 – Core Hardware & Supply Chain Kickoff

Mon, 16 Mar 2026 00:00:00 +0000

Overview

Week 5 marked the official transition from conceptual research into formal hardware and software development. Building on last week’s infrastructure setup, the team kicked off the physical design phase, steadily advanced the core codebase, and initiated supply chain planning.

What We Did

Altium Project Initialization: Formally launched the hardware design phase by initializing the VertexShell project in Altium Designer. We established the workspace, imported our validated schematic symbols, and set up the design rules for the upcoming PCB layout.
Codebase Development: Continued building out the core logic within our central GitHub repository. Focus remained on structuring data parsing pipelines and refining the integration between the sensor drivers and the primary application layer.
Bill of Materials (BOM) Kickoff: Started compiling the official Bill of Materials. We began identifying specific manufacturer part numbers for our core components (CO sensor, IMU, and LoRa module).

Key Decisions

Adoption of I2C as the Primary Sensor Bus: We officially selected I2C (Inter-Integrated Circuit) as the standard communication protocol for our sensor suite (CO sensor and IMU). This allows us to connect multiple peripheral devices using only two shared lines (SDA and SCL), vastly simplifying our Altium PCB routing and conserving valuable microcontroller GPIO pins compared to SPI or dedicated analog configurations.

Challenges

Footprint Verification: Initializing the Altium project required meticulous cross-referencing of component datasheets to ensure custom footprints match exact physical dimensions, preventing costly manufacturing errors during fabrication.

Next Steps

Complete the preliminary schematic capture in Altium and begin component placement on the board layout.
Integrate and test the first live sensor-read logic on the hardware development kit.
Finalize the first draft of the BOM for internal review and cost optimization.

VertexShell

Sun, 01 Mar 2026 14:16:31 +0000

VertexShell

A research project exploring [brief tagline — e.g., high-performance shell environments for vertex-based computation].

About the Project

VertexShell is a research project focused on [brief description of what VertexShell does]. The goal is to [state the main objective], enabling [target users or use cases] to [key benefit].

Feature 1 Short description of this feature.

Feature 2 Short description of this feature.

Feature 3 Short description of this feature.

Project Proposal

Download the full project proposal document below.

Week 4 – Outreach & Software Architecture

Tue, 24 Feb 2026 00:00:00 +0000

Overview

Week 4 shifted focus toward the “soft” infrastructure of the project. While the hardware research from Week 3 matured into a formal codebase, the team transitioned into high-level networking—both in terms of software repositories and professional industry connections.

What We Did

Sponsorship Meetings — Following up on last week’s outreach, we held our first formal meetings with potential corporate sponsors. We presented the VertexShell value proposition, focusing on how our integrated sensor suite (CO, IMU, and LoRa) addresses specific gaps in industrial site safety.

Week 2 – Requirements Engineering & System Design

Mon, 23 Feb 2026 00:00:00 +0000

Overview

The second week shifted the team’s focus from broad research to concrete planning. With the project scope firmly defined, the goal was to translate our initial vision into structured technical requirements and a system architecture that will guide the development of the ElectroCap.

What We Did

Requirements Gathering We held a structured workshop to define the functional and non-functional requirements of the helmet. This included setting thresholds for toxic gas detection (CO/VOC), defining the sensitivity for the EMF proximity alerts, and establishing the “self-healing” parameters for the LoRa mesh network.

Week 1 – Project Kickoff & Strategic Alignment

Wed, 18 Feb 2026 00:00:00 +0000

Overview

The first week marked the official start of the ElectroCap (VertexShell) project. The team came together to align on the vision, divide responsibilities, and lay the groundwork for the development phase. This shorter initial week (starting Feb 18) focused on structural organization and defining our unique value proposition.

What We Did

Scope Definition — We held our first full team meeting and collectively defined the project’s scope. The core objective was agreed upon: build an active smart helmet that eliminates “environmental blindness” in high-risk industrial environments (mines/construction) using sensor fusion and mesh networking.

Week 3 – Circuit Investigation & Outreach

Tue, 17 Feb 2026 00:00:00 +0000

Overview

Week 3 focused on the transition from conceptual diagrams to technical groundwork. The team pivoted to deep-dive component research and strategic industry outreach, ensuring the VertexShell project has both a solid hardware foundation and a path toward professional partnership.

What We Did

Circuit & Component Investigation — Conducted a comprehensive technical review of our core hardware.

Partnership Outreach — Drafted and dispatched our first round of formal emails to potential industry partners. These communications aim to establish early-stage collaborations and explore sponsorship opportunities.