Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2708876
date_generatedTue Jun 1 00:07:21 2021 os_platformWIN64
product_versionVivado v2019.2 (64-bit) project_id6336dfddf6db4fef991d3acb08d87a54
project_iteration1 random_ide1f8f39a2b0755188e9eac2c7b1bb6de
registration_ide1f8f39a2b0755188e9eac2c7b1bb6de route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-9300H CPU @ 2.40GHz cpu_speed2400 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram8.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=8 basedialog_ok=7 basedialog_yes=1 boardchooser_board_table=1
cmdmsgdialog_ok=3 constraintschooserpanel_add_existing_or_create_new_constraints=2 constraintschooserpanel_add_files=2 constraintschooserpanel_file_table=4
createnewdiagramdialog_design_name=1 filesetpanel_file_set_panel_tree=24 filesetpanel_messages=1 flownavigatortreepanel_flow_navigator_tree=2
gettingstartedview_create_new_project=1 hlistpanel_chooser_list=3 mainmenumgr_checkpoint=3 mainmenumgr_edit=8
mainmenumgr_export=1 mainmenumgr_file=10 mainmenumgr_flow=6 mainmenumgr_ip=4
mainmenumgr_open_block_design=2 mainmenumgr_project=5 mainmenumgr_reports=2 mainmenumgr_settings=2
mainmenumgr_text_editor=2 mainmenumgr_tools=6 msgtreepanel_message_view_tree=3 msgview_clear_messages_resulting_from_user_executed=1
multifilechooser_add_directories=6 pacommandnames_auto_update_hier=2 pacommandnames_create_top_hdl=1 pacommandnames_run_bitgen=1
pacommandnames_set_as_top=1 pacommandnames_simulation_run=2 paviews_code=1 paviews_project_summary=1
planaheadtab_refresh_changed_modules=1 projectfilechooserpanel_copy_sources_into_project=1 projectfilechooserpanel_new_script=1 projectnamechooser_choose_project_location=1
projectnamechooser_create_project_subdirectory=1 projectnamechooser_project_name=1 rdicommands_custom_commands=2 rdicommands_settings=2
rsbaddmoduledialog_module_list=12 selectmenu_highlight=1 settingsdialog_project_tree=4 srcchooserpanel_add_directories=2
srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3 srcchoosertable_src_chooser_table=3 srcfileproppanels_global_include=4 srcmenu_ip_hierarchy=1
srcmenu_refresh_hierarchy=1 systembuildermenu_add_module=7 systembuilderview_pinning=3 tclobjecttreetable_treetable=2
verilogoptionschooserpanel_specify_compilation_options_for_verilog=2
java_command_handlers
addsources=1 autoconnectport=42 createblockdesign=1 createtophdl=1
editcopy=5 editpaste=5 editundo=1 newproject=1
runbitgen=1 saversbdesign=1 settopnode=1 toolssettings=2
other_data
guimode=1
project_data
constraintsetcount=2 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=219 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=38 totalsynthesisruns=38

unisim_transformation
post_unisim_transformation
bscane2=3 bufg=7 carry4=823 dsp48e1=4
fdce=16050 fdpe=4 fdre=2998 fdse=215
gnd=159 ibuf=19 ibufds=2 idelayctrl=1
idelaye2=16 inv=3 iserdese2=16 lut1=459
lut2=2194 lut3=4995 lut4=6038 lut5=7480
lut6=17745 muxf7=460 muxf8=32 obuf=55
obufds=2 obuft=22 obuftds=4 oserdese2=44
plle2_adv=2 ramb18e1=30 ramb36e1=29 ramd32=366
rams32=122 srl16e=5 startupe2=1 vcc=1006
pre_unisim_transformation
bscane2=3 bufg=7 carry4=823 dsp48e1=4
fdce=16050 fdpe=4 fdre=2998 fdse=215
gnd=159 ibuf=3 idelayctrl=1 idelaye2=16
iobuf=16 iobufds=2 iserdese2=16 lut1=459
lut2=2194 lut3=4995 lut4=6038 lut5=7480
lut6=17745 muxf7=460 muxf8=32 obuf=55
obufds=1 obuft=6 oserdese2=44 plle2_adv=2
ram32m=61 ramb18e1=30 ramb36e1=29 srl16e=5
startupe2=1 vcc=1006

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=1 bram_ports_total=118 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=18546 srls_augmented=0
srls_newly_gated=0 srls_total=5

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=37 numhdlrefblks=37 numhierblks=0 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=37 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=BD
x_ipvendor=xilinx.com x_ipversion=1.00.a
bidirec/10
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/11
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/12
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/13
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/14
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/15
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/16
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/17
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/18
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/19
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/20
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/21
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/22
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/23
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/24
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/25
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/26
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/27
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/28
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/29
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/2
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/30
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/31
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/32
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/3
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/4
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/5
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/6
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/7
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/8
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bidirec/9
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bidirec x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
bootrom_wrapper/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=bootrom_wrapper x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
gpio_wrapper/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=gpio_wrapper x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
intcon_wrapper_bd/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=intcon_wrapper_bd x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
swerv_wrapper_verilog/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=swerv_wrapper_verilog x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
syscon_wrapper/1
core_container=NA iptotal=1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_iplibrary=module_ref x_ipname=syscon_wrapper x_ipproduct=Vivado 2019.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
biivrc-1=1 bufc-1=2 cfgbvs-1=1 check-3=2
dpip-1=8 dpop-1=4 dpop-2=4 dpor-1=16
reqp-1839=20 reqp-1840=20

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
dpir-1=152 lutar-1=4 reqp-1959=16 synth-6=3
timing-18=22 timing-6=2 timing-7=2 timing-9=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.068437 clocks=0.040527
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.109661 die=xc7a100tcsg324-1 dsp=0.000292 dsp_output_toggle=12.500000
dynamic=0.824810 effective_thetaja=4.6 enable_probability=0.990000 family=artix7
ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) i/o=0.397822
input_toggle=12.500000 junction_temp=29.3 (C) logic=0.015637 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.934471 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=csg324 pct_clock_constrained=42.000000 pct_inputs_defined=4
platform=nt64 pll=0.277971 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.024125 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=5.7 (C/W) thetasa=4.6 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=4.6 user_junc_temp=29.3 (C) user_thetajb=5.7 (C/W)
user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.179594 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.018344 vccaux_total_current=0.197938
vccaux_voltage=1.800000 vccbram_dynamic_current=0.004998 vccbram_static_current=0.001421 vccbram_total_current=0.006418
vccbram_voltage=1.000000 vccint_dynamic_current=0.175016 vccint_static_current=0.018821 vccint_total_current=0.193836
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.176477 vcco18_static_current=0.004000 vcco18_total_current=0.180477
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.001172 vcco33_static_current=0.004000 vcco33_total_current=0.005172
vcco33_voltage=3.300000 version=2019.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=7 bufgctrl_util_percentage=21.88
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=2 plle2_adv_util_percentage=33.33
dsp
dsp48e1_only_used=4 dsps_available=240 dsps_fixed=0 dsps_used=4
dsps_util_percentage=1.67
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=1 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=1
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=44 block_ram_tile_util_percentage=32.59
ramb18_available=270 ramb18_fixed=0 ramb18_used=30 ramb18_util_percentage=11.11
ramb18e1_only_used=30 ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=29
ramb36_fifo_util_percentage=21.48 ramb36e1_only_used=29
primitives
bscane2_functional_category=Others bscane2_used=3 bufg_functional_category=Clock bufg_used=7
carry4_functional_category=CarryLogic carry4_used=821 dsp48e1_functional_category=Block Arithmetic dsp48e1_used=4
fdce_functional_category=Flop & Latch fdce_used=15392 fdpe_functional_category=Flop & Latch fdpe_used=4
fdre_functional_category=Flop & Latch fdre_used=2935 fdse_functional_category=Flop & Latch fdse_used=215
ibuf_functional_category=IO ibuf_used=19 ibufds_functional_category=IO ibufds_used=2
idelayctrl_functional_category=IO idelayctrl_used=1 idelaye2_functional_category=IO idelaye2_used=16
inv_functional_category=LUT inv_used=3 iserdese2_functional_category=IO iserdese2_used=16
lut1_functional_category=LUT lut1_used=403 lut2_functional_category=LUT lut2_used=2274
lut3_functional_category=LUT lut3_used=4823 lut4_functional_category=LUT lut4_used=6101
lut5_functional_category=LUT lut5_used=7298 lut6_functional_category=LUT lut6_used=17433
muxf7_functional_category=MuxFx muxf7_used=460 muxf8_functional_category=MuxFx muxf8_used=32
obuf_functional_category=IO obuf_used=55 obufds_functional_category=IO obufds_used=2
obuft_functional_category=IO obuft_used=22 obuftds_functional_category=IO obuftds_used=4
oserdese2_functional_category=IO oserdese2_used=43 plle2_adv_functional_category=Clock plle2_adv_used=2
ramb18e1_functional_category=Block Memory ramb18e1_used=30 ramb36e1_functional_category=Block Memory ramb36e1_used=29
ramd32_functional_category=Distributed Memory ramd32_used=366 rams32_functional_category=Distributed Memory rams32_used=122
srl16e_functional_category=Distributed Memory srl16e_used=5 startupe2_functional_category=Others startupe2_used=1
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=460 f7_muxes_util_percentage=1.45
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=32 f8_muxes_util_percentage=0.20
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=244 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=33388 lut_as_logic_util_percentage=52.66 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=249 lut_as_memory_util_percentage=1.31 lut_as_shift_register_fixed=0 lut_as_shift_register_used=5
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=18546 register_as_flip_flop_util_percentage=14.63
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=33637 slice_luts_util_percentage=53.06
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=18546 slice_registers_util_percentage=14.63
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=244 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=33388 lut_as_logic_util_percentage=52.66 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=249 lut_as_memory_util_percentage=1.31 lut_as_shift_register_fixed=0 lut_as_shift_register_used=5
lut_in_front_of_the_register_is_unused_fixed=5 lut_in_front_of_the_register_is_unused_used=2751 lut_in_front_of_the_register_is_used_fixed=2751 lut_in_front_of_the_register_is_used_used=5823
register_driven_from_outside_the_slice_fixed=5823 register_driven_from_outside_the_slice_used=8574 register_driven_from_within_the_slice_fixed=8574 register_driven_from_within_the_slice_used=9972
slice_available=15850 slice_fixed=0 slice_registers_available=126800 slice_registers_fixed=0
slice_registers_used=18546 slice_registers_util_percentage=14.63 slice_used=9669 slice_util_percentage=61.00
slicel_fixed=0 slicel_used=6730 slicem_fixed=0 slicem_used=2939
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_used=595 unique_control_sets_util_percentage=3.75
using_o5_and_o6_fixed=3.75 using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=5
using_o6_output_only_fixed=5 using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=3 bscane2_util_percentage=75.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=1 startupe2_util_percentage=100.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=rvfpga -verilog_define=default::[not_specified]
usage
elapsed=00:02:23s hls_ip=0 memory_gain=830.527MB memory_peak=1194.145MB