gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM (bibtex)

by João Vieira, Nuno Roma, Gabriel Falcao and Pedro Tomás

Reference:

J. Vieira, N. Roma, G. Falcao, P. Tomás, "gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to DRAM", in IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), IEEE, nov, 2022, pp. 41–50.

Bibtex Entry:

@Inproceedings{sbac-pad22,
   author = "João Vieira and Nuno Roma and Gabriel Falcao and Pedro Tomás",
   title = "gem5-ndp: Near-Data Processing Architecture Simulation From Low Level Caches to {DRAM}",
   booktitle = "{IEEE} International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)",
   publisher = "IEEE",
   location = "Bordeaux - France",
   year = 2022,
   month = nov,
   pages = {41--50},
   doi = {10.1109/SBAC-PAD55451.2022.00015},
   url = {nfvr_pubs/sbac-pad22.pdf}
}