__Power Estimation in Digital
Circuits Using Implicit Enumeration Techniques__

As
power consumption becomes a major concern of integrated circuit and

system
designers, the need for adequate methods to quantify and

predict power is
growing significantly. However, the power dissipation

is generally
considered to be more difficult to compute than the

estimation of other
circuit parameters, like area and delay.

Existing approaches for
power estimation can be divided into two

categories: simulation based
methods and probabilistic methods.

Simulation based methods can model
very accurately the spatial and

temporal correlations present at the input
and internal signals, but

require the existence of a trace that accurately
matches the

conditions of operation of the system. These methods can be
very

inefficient if the trace is very long.

Probabilistic methods do
not require the existence of a trace and can

be used to characterize
circuits in a manner that is independent of

the inputs presented. However,
the most efficient approaches proposed

to date allow only for very
simplified models of temporal and spatial

correlations, and, therefore,
obtain estimates of limited accuracy.

In this thesis, we present a
probabilistic power estimation method

that accurately computes the power
dissipation for combinational and

sequential circuits at the logic level,
taking into account all

signal correlations for zero, unit and
generic

delay models.

Circuits are implicitly

characterized
in a way that is independent of a specific input trace. The

input
correlation modeling proposed is based on the definition of a

set of
functions that, in a simple but flexible way,

describe the input signal
statistics. In this method all functions

are manipulated using a binary
decision diagram based representation.

The power estimates are
obtained computing the switching activity by

implicitly enumerating the
number of

transitions for each node of the circuit.